Basis for Comparison | Synchronous Counter | Asynchronous Counter |
---|---|---|
Also called | Parallel Counter | Serial Counter |
Principle of operation | Each flip flop is triggered with same clock signal at the same time. | Each flip flop is triggered with different clock signal at different instant of time. |
Decoding errors | Not produced | Produced |
Operating speed | Fast | Comparatively slow |
Design | Complex | Simple |
Delay in signal propagation | Very Low | Comparatively high |
Count sequence | Not Fixed | Fixed |
Response to clock signal | Each flip-flop changes its state simultaneously. | There is no simultaneous change in the state of all flip flops with change in clock input. |
Overall settling time | Maximum settling time out of the settling time of each flip flop in the configuration. | Summation of settling time of each individual flip-flop. |
Flip-flop direct interconnection | Not Exist | Exist |
Applications | In moving machine controlling, alarms clocks, multiplexing circuits, etc. | In ring and johnson counters, frequency dividers, etc. |
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